The failure mode with no visible symptom

ESD protection in circuit design means deliberately routing electrostatic discharge energy away from sensitive silicon before it can do damage — using transient voltage suppression components at every external connector, a short low-impedance path to ground, and enclosure geometry that keeps sparks away from the board in the first place. Skip it, and you get the most frustrating warranty category there is: units that come back with the complaint "it just stopped working," no burn marks, no obvious cause, and no way to reproduce the failure on the bench.

The energy involved is easy to underestimate. Walking across carpet in dry winter air and touching a doorknob is a discharge of many thousands of volts. Modern semiconductor gate oxides are damaged by a few hundred volts, sometimes less. Every exposed pin, connector shell, button, and seam in your product is a potential entry point.

Two failure modes, and the dangerous one is not the obvious one

  • Catastrophic failure. The discharge punches through a thin insulating layer inside the chip or fuses an internal bond. The product dies on the spot. Painful, but honest — you find it immediately.
  • Latent damage. The discharge wounds the part without killing it. The unit passes final test, ships, sells, and fails weeks or months later in the customer's hands. Latent ESD damage spreads itself across time, defeats root-cause analysis, and quietly erodes a product's reputation before anyone connects the dots.

Because latent damage is invisible at the factory, you cannot test your way out of a weak ESD design. It has to be engineered in.

Where the discharge actually gets in

Map the entry points before you pick components. The usual suspects are USB and charging ports, headphone jacks, memory card slots, antenna feeds and any external RF connector, metal buttons and trim rings, exposed screw heads, battery contacts, and unshielded gaps in the plastic where a spark can jump to a nearby trace. Anything a human finger can reach — and anything within a few millimeters of something a finger can reach — is on the list.

Layer one: dedicated protection components

The workhorse is the TVS (transient voltage suppression) diode array. These cost cents in volume and clamp the transient to a safe level in nanoseconds. Selecting one comes down to three parameters:

  • Working voltage. The standoff voltage must sit above the line's normal operating level so the diode does not conduct in normal use, and the clamping voltage must stay below what the protected chip can survive.
  • Capacitance. This is where designs quietly fail. A general-purpose TVS with tens of picofarads of capacitance will wreck the signal integrity of USB high-speed or HDMI lines. High-speed interfaces need ultra-low-capacitance parts, typically well under one picofarad per channel.
  • Channel count and package. Multi-channel arrays in tiny packages let you sit the protection right at the connector instead of downstream.

Series resistors on slow signal lines, ferrites on power inlets, and gas discharge tubes or varistors on especially exposed lines round out the toolkit. Note that ESD protection and surge protection are different problems — a part sized for a human-body discharge will not survive a lightning-induced surge on a long outdoor cable run.

Layer two: the PCB layout does half the work

A correctly specified protection device in the wrong place protects nothing. Three rules cover most of it. Put the TVS physically first — between the connector and every other component on that net, never after a series element. Keep the path from the diode to ground short, wide, and via-rich, because a few nanohenries of inductance in that path will let the transient voltage spike far above the diode's rated clamp. And keep a continuous ground reference under the connector region rather than a stitched patchwork.

These are the same disciplines that determine whether a board passes radiated emissions, which is why stackup planning matters here too — see our guidance on choosing a PCB layer count and on EMC testing cost and scope. Get both right on the same layout pass and you avoid a redesign loop.

Layer three: mechanical design is free protection

The cheapest protection is the discharge that never reaches the board. Increase the creepage distance between external metal and circuitry, cover openings with plastic rather than leaving a spark gap, bond large metal cosmetic parts to chassis ground with a defined path, and avoid running sensitive flex cables directly behind a user-accessible seam. This only happens if the board and the housing are designed together rather than in sequence — the argument we make in our piece on electronics enclosure design. The same layout pass should also consider heat paths, since protection components near connectors compete for space with cooling features; see thermal management in electronics.

Why the chip's built-in protection is not enough

Every modern IC datasheet lists on-die ESD protection. That structure exists to survive handling on an automated assembly line in a static-controlled environment. It is not scaled for a charged user touching a connector on a dry day — the energy difference is an order of magnitude or more. The practical rule: every net that leaves the enclosure gets dedicated external protection, regardless of what the datasheet claims. Connector-heavy designs are exactly where this bites; our notes on designing USB-C into a new product cover the port that causes the most trouble.

How immunity is verified

Formal testing uses an ESD gun per the relevant IEC immunity standard: contact discharges to accessible conductive surfaces and air discharges to seams and openings, at several severity levels, with the highest levels in the multi-kilovolt range. The product must either keep operating or recover on its own without user intervention, depending on the performance criterion you declared. This runs at an accredited lab alongside the rest of the immunity suite.

Do a cheap pre-scan on your prototype first. Fixing an ESD weakness at the prototype stage costs a board revision; finding it after tooling and a production run costs a recall. Sequencing that check into the build plan is part of what the EVT, DVT and PVT stages are for, and it is worth budgeting into your PCB prototype cost from the start.

ESD damage starts before the product ships

Some field failures are born at the factory: parts handled without wrist straps, on non-dissipative work surfaces, or stored in the wrong bags. A professional assembly line runs a static-controlled environment — dissipative flooring, grounded tooling, ionizers where needed, and conductive packaging. Ask to see that program when you audit an assembly partner; it is as revealing as the solder paste inspection data.

The economics are stark. Designed in from the beginning, ESD protection adds a few dollars at most to a bill of materials. Discovered after tooling, it costs a board respin, a compliance retest, and a field population you no longer trust. More reliability engineering topics are collected in our electronics development hub.

If you are laying out a board with external connectors and want the ESD strategy reviewed before the first prototype order — or you have field returns with no explanation and suspect static — send us the details through our contact form and the Projects House engineering team will take a look.