The Boards Arrived and Nobody Wants to Plug Them In

You have five assembled prototypes on the bench and a wall adapter in your hand. This is the highest-risk ten minutes of the whole hardware phase. A reversed polarity, a swapped regulator feedback divider, or a solder bridge under a BGA can destroy the entire lot in under a second, and a respin costs two to four weeks plus assembly, which usually lands between 2,000 and 8,000 USD depending on stencil and component reorders.

Bring-up is a procedure, not an event. Written down, followed in order, and logged. Experienced hardware engineers rarely lose boards, not because they are luckier but because they never skip steps.

Before Any Voltage: Inspect and Ohm It Out

Set one board aside untouched as a golden reference in case you need to compare later. Then, on the first unit:

  • Visual inspection under a 10x loupe or stereo microscope. Look for tombstoned passives, bridges on fine-pitch parts, components missing against the assembly drawing, and pin-1 orientation on every IC, diode, and electrolytic. Reversed connectors and rotated ICs are the most common assembly errors and the most destructive.
  • Continuity and short check. In resistance mode, measure every power rail to ground. Near zero ohms means stop. Healthy rails read from tens of ohms up into the kilohms depending on bypass capacitance and load. Note the values; they are your reference for the next boards.
  • Input protection check. Verify the reverse polarity FET or diode is oriented correctly and the input fuse or PTC is populated. If you kept an unpopulated PCB, ohm out its rails too, which isolates fabrication shorts from assembly shorts.

If the board came back with obvious workmanship problems, resolve that with the assembler before burning a week debugging their mistake. What a reasonable low-volume build should cost is covered in PCB prototype cost.

First Power: Current-Limited, Staged, and Watched

Never bring up a new board on a wall adapter. Use a bench supply with adjustable current limit, and set the limit low, typically 50 to 100 mA for a small board, just above the expected quiescent draw. Then raise the voltage slowly from zero while watching the current meter.

What you want: current in the tens of milliamps and the supply never hitting its limit. What tells you to stop: the supply drops into constant-current mode at low voltage, current climbs steadily with voltage, or anything gets warm. Keep a fingertip or thermal camera on the board during the first ramp, since a component heading for failure warms noticeably first.

Bring up the power tree one rail at a time from the input inward, verifying each regulator's output before enabling the next. Measure the actual voltage, not just presence: a 3.3 V rail sitting at 3.05 V means a feedback divider error or a regulator in dropout, and it will cause intermittent faults for months if you accept it. Check ripple with a short ground spring rather than a long clip lead, which fabricates noise that is not there. Why switching and linear rails misbehave differently is worked through in DC-DC converter vs LDO.

Check power sequencing too. Many SoCs and FPGAs require rails to come up in a defined order within a defined window, and violating it can latch up the part or leave it in an undefined state that looks like a firmware bug for days.

Waking the Processor

With rails verified, the next milestone is a debugger connection. In order:

Confirm the reset line reaches its inactive level and is not held low by a watchdog or supervisor. Confirm the crystal is running, probing the output side only, since touching the input side often stops a low-power oscillator. Then attach the SWD or JTAG probe and read the device ID. Getting an ID back is the real first success: power, ground, clock, reset, and debug pins are all correct. Tooling choices are compared in embedded debugging tools.

Then flash the smallest possible program: toggle one GPIO tied to an LED or, better, to a scope probe. Resist the urge to load the full application. A blinking LED at a measured frequency proves the clock tree configuration is right, and a wrong frequency here explains every timing problem you would otherwise chase later. If the board has a bootloader, bring it up before the application so you have a recovery path that does not require the debugger, a pattern explained in bootloaders in embedded products.

One Subsystem at a Time

Now work outward, and change exactly one thing between tests. A sensible order is internal buses first, then external interfaces, then radios and power-hungry loads.

For each bus, read a known register from a known device and compare to the datasheet's reset value. On I2C, run an address scan before anything else; a device that does not enumerate is a wiring, pull-up, or address-strap problem, not a driver problem. On SPI, check clock polarity and phase on a scope rather than guessing, and confirm chip select actually toggles. The failure signatures for each bus are laid out in I2C vs SPI vs UART.

Leave anything that draws serious current, such as motors, heaters, and transmit-mode radios, for last, and bring them up with the current limit still active. Also confirm that inputs exposed to the outside world have their protection populated and correct before you connect anything external, because the first ESD event on an unprotected line will find you. The rationale is in ESD protection in circuit design.

Log Everything, Because There Will Be a Next Revision

Keep a bring-up log with a row per board: serial number, measured rail voltages, current draw at each stage, every rework applied, and every anomaly with its resolution. Photograph blue-wire fixes and cut traces immediately, because an undocumented rework on prototype three becomes a phantom bug on prototype four.

Mark findings into the schematic and layout in real time rather than reconstructing them later. Typical first-spin outcomes are a handful of these: a missing pull-up, an inverted enable, a footprint error, an inadequate copper pour on a high-current path. That list is exactly what the next build fixes, and treating bring-up as the formal gate between revisions is why the phase structure in EVT, DVT, and PVT exists.

Budget one to two weeks of engineering time for a moderately complex board, longer with a radio or a high-speed bus. Teams that schedule two days are the ones that skip the current limit.

Bring Up Your Board With Someone Who Has Done It

Projects House designs and brings up electronics, from the first current-limited power-on through interface debug and the rework list that defines the next spin. Send your schematic, layout, and assembly status through our contact form and we will plan the bring-up with you.